1. Field of the Invention
The present invention generally relates to metal-oxide-semiconductor field effect transistor (MOSFET) designs, and more particularly, to a patterning method and design for MOSFET device gates.
2. Description of the Related Art Density, scalability, and manufacturability are important considerations in metal-oxide-semiconductor field effect transistor (MOSFET) designs. As MOSFET device miniaturization proceeds, the lithography needed to produce small device features becomes difficult. One concern is how the depth of focus of lithographic systems decreases as the size of the features to be printed decreases. This means that where small features are to be distinguished, topography on the wafers much be kept to a minimum. In miniatured devices, many elements of the device fabrication must change. Low resistance contacts to the MOSFET source and drain areas become difficult to make, and self-aligned, elevated source/drain structures look attractive for reducing source/drain series resistance and short channel effects (J. Y. Tsai and C. M. Osburn, Proc. of 6th Int. Symp. Ultralarge Scale Integration Sci. Tech., Montreal, CA, May 5-9, 1997, p. 429). Other materials that may be useful in scaled devices are high-k dielectrics like metal oxides, for example, which can raise the MOSFET gate capacitance without increasing the gate leakage current and without compromising the device breakdown characteristics.
Using metallic materials for the MOSFET gate conductors are also an important area of research, as a metal gate can reduce the gate resistance and gate delay. However, both of these materials require that processing temperature remain low, and so the materials cannot be used until after the doped source/drain areas are annealed. This problem has led to the idea of creating a dummy or stand-in MOSFET gate structure (e.g. out of nitride) instead of a real gate at the appropriate step in the process. After dummy formation, the steps of processing the source/drain regions, removing the dummy gate, depositing or growing a high-k gate dielectric, and depositing a metallic gate material are performed.
It is necessary that the new gate be self-aligned to the position and size of the dummy gate, which has led to the development of a "damascene" gate process. In the "damascene" process, the dummy gate is formed, source/drain doping is performed, a dielectric is formed and CMP is performed to planarize to the level of the topgate. Then, the dummy gate is removed, followed by forming a well, depositing the gate dielectric and gate conductor and planarizing with CMP to fill the well left behind (T. Saito, A. Yagishita, S. Inumiya, K. Nakajima, Y. Akasaka, Y. Ozawa, H. Yano, K. Hieda, K. Suguro, T. Arikado, K. Okamura, Jpn. J. Appl. Phys. 1, vol. 38, no. 4B, April 1999, p. 2227).
The result of the "damascene" gate process is an improved MOSFET device with improved and reduced device topography over a conventional MOSFET and enables the easy use of a replacement gate, but has no advantages with respect to source/drain resistance over a conventional device. In Saito's design, contacts to the source/drain must be made using an additional patterning step and cutting through the planarized oxide to reach the source/drain silicide. This means that a significant overlay tolerance must be included so that the source/drain contacts do not touch the gate.
One drawback to the Saito design is that it does not provide for a reduction in overall device size as compared to a conventional gate design. The additional patterning step and cutting require inclusion of a lithography alignment tolerance in the spacing between the source and drain contacts with respect to the gate. The lithography alignment tolerance acts as a buffer between the gate and the contact necessary to insure there not be a short between the gate and the contact when cutting the contacts. As a result of the alignment tolerance, the minimum device size is increased.
A second drawback to the Saito design is the differing source metal-to gate and drain metal-to-gate capacitances. During the additional patterning step, perfect positioning (i.e., equal distance between the gate and the metal fill on either side) is nearly impossible. As a result of the differing distances, the source/drain metal-to-gate capacitances will not be equal.